Building a SDRAM 128MB v2.9 for Mister FPGA
Versión 2.9 of the SDRAM module for Mister corrects many design issues from previous RAM modules. This new version uses more power pins, has better decoupling and uses a linear voltage regulator and a SMD connector.
I've used the X7R capacitors with the highest voltage rating - at a reasonable price - for 0805 footprint and preferably from good brands like Taiyo Yuden or Samsung, bought at Mouser to be sure of their authenticity.
The 2x20 SMD connector is probably Phoenix Contact 1156904 or Samtec SMH-120-02-G-D, but the one I used comes from RTLECS shop at Aliexpress.
|U4||LM1117F-3.3 SOT-89 (SOT-89-3)|
|Conector||Female header SMT 2.54mm 2x20 pins|
When you upload SDRAM PCB gerbers to JLCPCB select impedance control JLC7628. This is the order for the capacitors from top to bottom, taken from the official forum:
- Fila superior
- 10µF · 0.1µF · 1µF · 10µF · 0.1µF · 1µF
- Fila inferior
- 10µF · 1µF · 1µF · 10µF · 10µF · 1µF · 1µF · 10µF
The capacitor next to
U4 is 10µF.
Using the adequate ESD protection, the SDRAM module is inserted into the Terasic DE10-Nano using the thumbs to avoid PCB bending. In order to extract the module you need to do a back and forth movement while gently pulling. This is explained with animated gifs in the official documentation.